Crosstalk Delay Analysis in Very Deep Submicron VLSI Circuits

The evolution of Integrated Circuit designing has been a real game changer in the field of VLSI system in the past quarter century. Very deep sub-micron (VDSM) technologies embracing sub-100nm wafer design technologies, to take advantage of the superior integration possibilities. At these technologies, many phenomena affect gate, path delay or wire delays. Now a days, crosstalk noise or crosstalk delay has become a challenging design issue due to growing integration density with every technology node. Since, crosstalk in interconnect had a great impact on reliability and performance of IC, that’s why there is need to minimize this effect to maintain signal integrity in interconnect. In this paper, Crosstalk in proposed model can be minimized using various techniques such as buffer insertion (CMOS inverter and Schmitt trigger as a buffer), insertion along with shielding, skewing, shielding and skewing together, aspect ratio scaling and also using physical separation between interconnects. Keywords-aspect ratio scaling, buffer insertion, coupling capacitance, Crosstalk, CMOS buffer, Schmitt trigger,signal integrity,shielding.